High frequency power conversion is per se the most enticing solution to the demands for increasing high feedback control dynamics and reducing printed circuit board (PCB) space in low-voltage high-current applications, such as voltage regulator modules (VRMs) or point of load (PoL).
High switching frequency operation is however detrimental for the converter efficiency, which requires to be kept high especially in these applications. High efficiency is therefore a major obstacle for increasing the switching frequency operation. This in turn tremendously influences the design guidelines of the converter and particularly the switch devices, which have to feature both low conduction resistance and high switching performance.
The most extended converter topology in VRM and PoL applications is the synchronous buck. In this converter, two power switching loss mechanisms are of important relevance: reverse recovery and gate bounce of the synchronous rectifier metal-oxide-semiconductor field effect transistor (sync MOSFET or sync FET). See the article “Quantification of Switching Loss Contributions in Synchronous Rectifier Applications” by Thomas Duerbaum, Tobias Tolle, Reinhold Elferich and Toni Lopez, 10th European Conference on Power Electronics and Applications EPE, September 2003, Toulouse, France, paper 786. These two power switching loss mechanisms generate heat in both synchronous MOSFETs and control MOSFETs, thereby reducing the efficiency of the converter.
A well-known solution exists which mitigates reverse recovery by means of intelligent drivers with adaptive dead time control schemes. This solution has been proven to work effectively only in integrated modules. See for example information on the World Wide Web at semiconductors.philips.com/pip/PIP212-12M.html, and prior art article “Challenges of Integrated Power Trains” by Philip Rutter, Intel Symposium 2004.
Another more recent solution, see WO 2004/114509 A1, although particularly meant for reduction of electromagnetic interference (EMI), takes advantage of the so-called “body effect” present in MOSFETs. See also the article “The influence of body effect and threshold voltage reduction on trench MOSFET body diode characteristics” by G. M. Dolny, S. Sapp, A. Elbanhaway, C. F. Wheatley, ISPSD 2004, pages 217 to 220, or the article “Third Quadrant Output Characteristics in High Density Trench MOSFETs” by Thomas Duerbaum, Toni Lopez, Reinhold Elferich, Nick Koper, and Tobias Tolle, 11th International Power Electronics and Motion Control Conference EPE-PEMC, September 2004, Riga, Latvia, paper A14370, in order to effectively eliminate reverse recovery by means of series diodes added to the gate circuit.
Based on this idea a new FET device which integrates the series diodes and the MOSFET in a single package will become a product for the automotive industry, featuring low electromagnetic interference (EMI) switching behavior.
The above solutions, although mitigating reverse recovery, may worsen gate bounce. In case of this FET device, gate bounce can be so much worse that the overall power loss may become higher than that in a conventional solution in case of high switching frequency applications.
An eligible technique to minimize gate bounce aims at making a device structure with a low ratio of Crss (=miller feedback capacitance) to Ciss (=lumped input capacitance or stated input capacitance), i.e. a device comprising a low susceptibility to gate bounce. A low impedance gate path further helps minimize this lossy effect.
U.S. Pat. No. 5,929,690 proposes a device, which is optimized to exploit the “body effect” by means of modifying parameters of the semiconductor technology (oxide thickness, doping profile, . . . ) which may compromise other relevant device parameters, such as capacitances and the on-state drain-to-source resistance RDS (on). In this context, U.S. Pat. No. 5,929,690 proposes to lower the nominal threshold voltage to effectively exploit the “body effect”. Apart from that, U.S. Pat. No. 5,929,690 completely neglects the gate bounce effect, which may significantly generate switching power losses in state of the art power MOSFETs, particularly when lowering the threshold voltage so as to exploit the “body effect”. This is so much so, that the benefits of the “body effect” may not compensate the increase of the gate bounce related losses in prior art power MOSFETs.
Regarding the technological background of the present invention, reference can finally be made to
U.S. Pat. No. 6,421,262 B1 proposing an active switch which is self-controlled,
U.S. Pat. No. 6,819,149 B2 employing a timing control to minimize the voltage ringing at the switch node voltage of a half-bridge; this timing control causes spurious shoot-through, thereby generating extra losses in the switched circuit so as to reduce voltage ringing,
US 2005/0047177 A1 which is exclusively applicable to A[lternating] C[urrent]/D[irect] C[urrent] converters for power mains, particularly to forward converters.